Verilog

Verilog is a hardware description language (HDL). It is is primarily used for designing FPGAs and ASICs and has a syntax similar to the C programming language. It includes constructs for defining modules, data types, and control structures.

SystemVerilog is an extension that adds more features for verification and design.

Data Types

Wire: Connections between components.
Reg: Storage elements (like flip-flops).
Integer: Whole numbers
Real: Floating-point numbers.

Hello World

// define a module with three ports (1 output, 2 input)
module hello_world (
    output reg led,     // Output signal (e.g., LED)
    input clk,          // clock input
    input reset         // reset input
);

    initial begin // set initial state
        led = 0;
    end

    // Always block to toggle the LED on clock edges
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            led <= 0;    // Reset LED to off
        end else begin
            led <= ~led; // Toggle LED state
        end
    end

endmodule

Abstraction Levels

Gate Level

2-to-1 Multiplexer

module multiplex_gatelevel(A,B,X,out1);
    input A, B, X;
    output out1;

    wire not_x;
    wire out_and1, out_and2;

    not not1(not_X, X);

    and and1(out_and1, not_X, A);
    and and2(out_and2, X, B);

    or or1(out1, out_and1, out_and2);
endmodule

Dataflow Level

2-to-1 Multiplexer

module multiplex_datalevel(A,B,X,out1);
    input A, B, X;
    output out1;

    assign out1 = ((~X&A)&A)|(B&X);
endmodule

Behavioural Level

2-to-1 Multiplexer

module multiplex_behavior(A,B,X,out1);
    input A, B, X;
    output reg out1;

    always@(*) begin
        if (X == 0)
            out1 = A;
        else
            outl = B;
    end

endmodule

Software

ModelSim

Windows, Linux
Commercial
Target Hardware: FPGAs, ASICs
Supported HDLs: Verilog, VHDL
Features:
- Provides a GUI and supports mixed-language simulation
- Waveform viewing, debugging capabilities

Vivado Design Suite

Windows, Linux
Commercial
Target Hardware: FPGAs (Xilinx)
Supported HDLs: Verilog, VHDL
Features:
- Design suite for FPGA development
- Integrated design environment with debugging tools

Quartus Prime

Windows, Linux
Commercial (Free Lite edition)
Target Hardware: FPGAs (Intel)
Supported HDLs: Verilog, VHDL
Features:
- Synthesis, simulation, and programming tools for Intel FPGAs

Icarus Verilog

Windows, Linux, macOS
Free and Open-source
Target Hardware: FPGAs, ASICs, General
Supported HDLs: Verilog
Features:
- Verilog simulation tool used for educational purposes and small projects.
- Command-line interface and integration with GTKWave for waveform viewing.

Synopsys VCS

Windows, Linux
Commercial
Target Hardware: ASICs
Supported HDLs: Verilog, SystemVerilog
Features:
- Verilog simulator that is part of the Synopsys suite of EDA tools
- High-performance simulation with debugging capabilities

Verilator

Windows, Linux, macOS
Free and Open-Source
Target Hardware: FPGA, ASIC, General
Supported HDLs: Verilog
Features:
- Converts Verilog code into C++ or SystemC for simulation.
- High-performance simulation and integration with other C++ tools