Hardware Description Language (HDL)

A Hardware Description Language (HDL) is a specialized programming language used to describe the design of electronic circuits. It can be used to model complex digital systems from high-level algorithmic descriptions to low-level gate-level representations.

HDLs can be used to design, simulate, and verify FPGAs (Field-Programmable Gate Arrays) and ASICs (Application-Specific Integrated Circuits). They can then be synthesized into actual physical circuits.

The most widely used HDLs are Verilog and VHDL.

Abstraction Levels

HDLs work at different levels of abstraction (from high to low):

Behavioral Level: What the system does (e.g., algorithms, data flow)
Register Transfer Level (RTL): How data moves between registers
Structural Level: Describes physical components and their interconnections

Compilation

The final output of an HDL is a hardware representation. The process involves multiple stages, including synthesis, simulation, and implementation

Elaboration:

Process of resolving all the design units, instantiating modules
Prepares the design for simulation.

Simulation:

Code is simulated to verify its functionality
Interprets the HDL code and executes it to produce waveforms and outputs

Synthesis:

Goal of compilation is to synthesize it into a hardware representation
Synthesis converts code into a gate-level representation

Implementation:

Hardware representation is mapped to target hardware (FPGA or ASIC)
Includes place-and-route processes
Physical locations of components and routing paths are established

Hardware Representatoin

The main hardware representations include:

Netlist: Description of circuit in terms of logic gates and interconnections.
Gate-Level Representation: Type of netlist using standard logic gates.
RTL Representation: Abstract representation describing data flow.
Technology Mapping: Netlist mapped to specific technology libraries
Timing Constraints: Information about timing requirements and delays

These outputs are used in the design flow, such as place-and-route and physical implementation.

File Formats

Netlist Formats

EDIF (Electronic Design Interchange Format): Standard format for netlists
Verilog Netlist: Netlist in Verilog format
VHDL Netlist: Netlist in VHDL format

Simulation Files

VCD (Value Change Dump): Stores simulation results, capturing changes in signal values over time. Used for waveform viewing.
WLF (Waveform Log File): Stores waveform data for analysis.

Synthesis Reports

Text or HTML files that include resource utilization and timing analysis

Implementation Files

Bitstream Files: Binary file containing FPGA configuration data
- BIT: A bitstream file format used by Xilinx FPGAs.
- SOF (SRAM Object File): Configuration file used by Intel (Altera) FPGAs.
GDSII (Graphic Data System II): Used for the physical layout of ASICs

Constraint Files

SDC (Synopsys Design Constraints): Specifies timing and design constraints for synthesis and implementation tools.