HDLs work at different levels of abstraction (from high to low):

• Behavioral Level: What the system does (e.g., algorithms, data flow)
• Register Transfer Level (RTL): How data moves between registers
• Structural Level: Describes physical components and their interconnections

The final output of an HDL is a hardware representation. The process involves multiple stages, including synthesis, simulation, and implementation

Elaboration:

• Process of resolving all the design units, instantiating modules
• Prepares the design for simulation.

Simulation:

• Code is simulated to verify its functionality
• Interprets the HDL code and executes it to produce waveforms and outputs

Synthesis:

• Goal of compilation is to synthesize it into a hardware representation
• Synthesis converts code into a gate-level representation

Implementation:

• Hardware representation is mapped to target hardware (FPGA or ASIC)
• Includes place-and-route processes
• Physical locations of components and routing paths are established

The main hardware representations include:

• Netlist: Description of circuit in terms of logic gates and interconnections.
• Gate-Level Representation: Type of netlist using standard logic gates.
• RTL Representation: Abstract representation describing data flow.
• Technology Mapping: Netlist mapped to specific technology libraries
• Timing Constraints: Information about timing requirements and delays

These outputs are used in the design flow, such as place-and-route and physical implementation.

Netlist Formats

• EDIF (Electronic Design Interchange Format): Standard format for netlists
• Verilog Netlist: Netlist in Verilog format
• VHDL Netlist: Netlist in VHDL format

Simulation Files

• VCD (Value Change Dump): Stores simulation results, capturing changes in signal values over time. Used for waveform viewing.
• WLF (Waveform Log File): Stores waveform data for analysis.

Synthesis Reports

• Text or HTML files that include resource utilization and timing analysis

Implementation Files

• Bitstream Files: Binary file containing FPGA configuration data
  • BIT: A bitstream file format used by Xilinx FPGAs.
  • SOF (SRAM Object File): Configuration file used by Intel (Altera) FPGAs.
• GDSII (Graphic Data System II): Used for the physical layout of ASICs

Constraint Files

• SDC (Synopsys Design Constraints): Specifies timing and design constraints for synthesis and implementation tools.

Verilog is a hardware description language (HDL). It is is primarily used for designing FPGAs and ASICs and has a syntax similar to the C programming language. It includes constructs for defining modules, data types, and control structures.

SystemVerilog is an extension that adds more features for verification and design.

// define a module with three ports (1 output, 2 input)
module hello_world (
    output reg led,     // Output signal (e.g., LED)
    input clk,          // clock input
    input reset         // reset input
);

    initial begin // set initial state
        led = 0;
    end

    // Always block to toggle the LED on clock edges
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            led <= 0;    // Reset LED to off
        end else begin
            led <= ~led; // Toggle LED state
        end
    end

endmodule

module multiplex_gatelevel(A,B,X,out1);
    input A, B, X;
    output out1;

    wire not_x;
    wire out_and1, out_and2;

    not not1(not_X, X);

    and and1(out_and1, not_X, A);
    and and2(out_and2, X, B);

    or or1(out1, out_and1, out_and2);
endmodule

module multiplex_datalevel(A,B,X,out1);
    input A, B, X;
    output out1;

    assign out1 = ((~X&A)&A)|(B&X);
endmodule

module multiplex_behavior(A,B,X,out1);
    input A, B, X;
    output reg out1;

    always@(*) begin
        if (X == 0)
            out1 = A;
        else
            outl = B;
    end

endmodule

VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a hardware description language (HDL). It is used to design and simulate FPGAs and ASICs.

VHDL has a more verbose and strongly typed syntax compared to other HDLs like Verilog.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hello_world is
    Port (
        led    : out STD_LOGIC;  -- output signal (e.g., LED)
        clk    : in  STD_LOGIC;  -- clock input
        reset  : in  STD_LOGIC   -- reset input
    );
end hello_world;

architecture Behavioral of hello_world is
begin

    process(clk, reset)
    begin
        if reset = '1' then
            led <= '0';  -- Reset LED to off
        elsif rising_edge(clk) then
            led <= not led;  -- Toggle LED state
        end if;
    end process;

end Behavioral;