VHDL (VHSIC Hardware Description Language)

VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a hardware description language (HDL). It is used to design and simulate FPGAs and ASICs.

VHDL has a more verbose and strongly typed syntax compared to other HDLs like Verilog.

Data Types

Bit: 0 or 1
Bit Vector: Array of bits
Integer: Whole numbers.
Real: Floating-point numbers
Enums: Custom data types with named values

Hello World

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hello_world is
    Port (
        led    : out STD_LOGIC;  -- output signal (e.g., LED)
        clk    : in  STD_LOGIC;  -- clock input
        reset  : in  STD_LOGIC   -- reset input
    );
end hello_world;

architecture Behavioral of hello_world is
begin

    process(clk, reset)
    begin
        if reset = '1' then
            led <= '0';  -- Reset LED to off
        elsif rising_edge(clk) then
            led <= not led;  -- Toggle LED state
        end if;
    end process;

end Behavioral;